This invention relates to an output circuit (output buffer). More particularly, it relates to a technique which is especially effective when applied to, for example, a plurality of output circuits that are disposed in a digital processor constructed of a gate-array integrated circuit and that are simultaneously brought into operating states in accordance with predetermined timing signals.
In the art, there are known gate-array integrated circuits which include a plurality of output circuits adapted to be simultaneously brought into operating states, and which construct a digital processor such as computer. In addition, push-pull output circuits for such output circuits are described in, for example, "MOS INTEGRATED CIRCUITS," pp. 246-249, issued by Robert E. Krieger Publishing Company, U.S., in 1979.
Shown in FIG. 11 is a circuit diagram of an example of a tri-state output circuit studied by the inventors prior to the present invention. This circuit employs the aforementioned push-pull output circuit. This output circuit includes (n+1) data output buffers DOB0-DOBn which are simultaneously brought into operating states in accordance with an output control signal .phi.oe by way of example, and an output buffer OBc which serves to deliver a sequence control signal CTa. Each of the output buffers includes output MOSFET's Q21 and Q22 of the N-channel type which are connected in series form between the power source voltage Vcc and ground potential of the circuitry. The gates of the output MOSFET's Q21 and Q22 of each output buffer are respectively supplied with internal signals which are selectively formed according to the output control signal .phi.oe and a corresponding one of inverted internal output signals Do0 -Don. Thus, when the output control signal .phi.oe is set at a high level and the corresponding one of the inverted internal output signals Do0-Don is set at a low level of logic "1," the output MOSFET Q21 is selectively brought into its "on" state and delivers an output signal of high level to a corresponding one of output terminals. On this occasion, the output MOSFET Q21 constitutes a source-follower circuit whose load is the output MOSFET Q22. On the other hand, when the output control signal .phi.oe is set at the high level and the corresponding one of the inverted internal output signal Do0-Don is set at a high level of logic "0," the output MOSFET Q22 is selectively brought into its "on" state and delivers an output signal of low level to the corresponding one of the output terminals. On this occasion, the output MOSFET Q22 constitutes a source-grounded amplifier circuit whose load is the output MOSFET Q21.
Meanwhile, in the output buffer OBc, a NOR gate circuit NOG9 and a NAND gate circuit NAG7 are normally held in their transferring states. Therefore, the output MOSFET's Q21 and Q22 of the output buffer OBc selectively deliver the sequence control signal CTa of low level or high level from an output terminal CTa in accordance with an inverted internal output signal Co. This sequence control signal CTa is used for, e.g., selecting the next instruction step of the digital processor.
The output buffers DOB0-DOBn and OBc have resistive, inductive and capacitive loads coupled to the output signal lines thereof through the output terminals D0-Dn and CTa. In addition, these output buffers are supplied with the ground potential of the circuitry through a ground potential feed line GND, to which a resistive load Rs, an inductive load Ls, etc. similar to the above are coupled. Further, the digital processor or the like including these output buffers has the tendency that, as the operating speed thereof is raised, the size of each output MOSFET is enlarged to lower the conductance, namely, the "on" resistance thereof, to thus heighten the driving ability thereof.
For this reason, in a case where, by way of example, a plurality of data output buffers are simultaneously brought into the operating states to turn "on" a plurality of output MOSFET's all together, a sudden change in current arises on a power source voltage feed line or the ground potential feed line GND. This change is conspicuous, for example, when the output signals of logic "0" or low level are delivered from all the data output buffers. As illustrated in FIG. 12, the change develops power source noise of comparatively large magnitude ascribable to the parasitic inductance Ls, etc. on the ground potential feed line GND. More specifically, when the output MOSFET's Q21 of the data output buffers DOB0-DOBn are turned "on" all together, the load capacitances coupled to the respective output signal lines are discharged all at once, and the resulting discharge currents flow to the ground potential feed line GND. On this occasion, the output MOSFET's Q21 of the respective data output buffers are brought into stable "on" states because the gate-source voltages thereof are rendered substantially constant irrespective of the drain voltages thereof. Accordingly, the ground potential feed line GND undergoes the following noise: EQU .DELTA.V=Ls .times. Ig/.DELTA.t
where Ls denotes the parasitic inductance thereof, and Ig denotes the discharge currents. This noise of the ground potential feed line GND further develops noise exceeding the maximum specification V.sub.OL of the low-level output signal in, for example, the low-level sequence control signal CTa which is delivered from the output buffer OBc arranged near the data output buffers DOB0-DOBn. In consequence, an instruction control operation in the instruction control circuit of the digital processor or the like is caused to err, and the malfunction of the whole processor is incurred.
In order to cope with this drawback, the inventors considered the addition of Miller capacitors C as indicated by dotted lines in FIG. 11, before the present invention. As an experimental result, however, an abnormal peak appeared in the output signal level due to the Miller capacitor as indicated by a dotted line in FIG. 12. Besides, because the Miller capacitors must be of comparatively large size, the layout efficiency of the output circuit lowered, and the high-density integration thereof was hampered.
The solution of the problems of the output circuits as stated above is required especially for gate-array integrated circuits etc. which need to be standardized and in each of which a power source voltage feed line and a ground potential feed line cannot be laid in a functionally-divided fashion.